The present invention generally relates to direct memory access controllers, and more particularly to a direct memory access controller which controls a direct data transfer.
In a data processing apparatus such as a computer system, a direct memory access controller (DMAC) is used to reduce data transfer time between a memory and an input/output (I/O) interface and between a memory and a memory which are coupled to a common system bus. According to the direct memory access (DMA), the data can be transferred directly between the memory and the I/O interface and between the memory and the memory under a control of the DMAC without passing the data through a central processing unit (CPU) which is used as a peripheral device coupled to the system bus.
There are DMACs which have a plurality of channels so as to independently make a data transfer in each channel. In this case, each channel generally informs the CPU of the end of the data transfer by an interrupt. The CPU executes an interrupt acknowledge cycle responsive to the interrupt and executes a process routine with respect to the end of the data transfer in accordance with an interrupt vector returned from the DMAC. Accordingly, when an interrupt request is made in a plurality of channels, there is a need to select one of the channels and supply the interrupt vector of the interrupt request to the CPU.
Conventionally, the DMAC is assigned priorities to the plurality of channels in advance. Hence, when the interrupt request is made in a plurality of channels, a channel having the highest priority of the channels is selected and the interrupt vector of the interrupt request is supplied to the CPU.
This means that when a data transfer is ended in a channel having a low priority due to an exception primary factor such as a bus error and a data transfer is normally ended in a channel having a high priority approximately at the same time, the conventional DMAC respects the channel having the high priority and supplies to the CPU an interrupt vector of the channel which has the high priority and in which the data transfer is normally ended. For this reason, there are problems in that there is a delay in providing the CPU with the primary factor related to the system failure such as a bus error so that a secondary failure may occur due to this delay.